Flight Readiness Technology Assessment NASA EEE Parts Program Assessment of DRAM Reliability from Retention Time Measurements

It was attempted to assess the reliability of DRAMs at the package level. Since the most critical function of a DRAM storage cell is to retain the charge which represents its state, data retention was measured at nominal conditions as a function of refresh time on several 5-V, 4-Mbit memories and one 3.3-V, 16-Mbit memory. Model distributions were fitted to the failure distributions and extrapolated to the time to first failure t 1. These times t 1 are an indication of the maturity of each product. The ratio t 1 /t r , where t r is the maximum specified refresh time, is a figure of merit for tolerance to degradation of the product. In the second phase of the project, the retention time distributions were measured at temperatures down to-30 °C and activation energies derived. The memories were then stressed at elevated voltages and temperatures for times up to 18 hours while they were continually refreshed at normal rate. After each stress a memory was subjected to a checkerboard test at nominal conditions. Then the retention times were remeasured at normal voltage and low temperatures. The hypothesis for this experiment, based on some literature reports, was that the leakage of the dielectric of the storage capacitors would be increased by charge injection under stress before breakdown of the dielectric. Low temperature was applied during measurement to separate this effect, which is based on tunneling through the dielectric, from leakage to the substrate and through the pass transistor, which is based on thermal carrier generation. The results are as follows: One type of 4-Mbit memory failed the checkerboard test in a regular pattern before any degradation of retention times could be detected. The other type, by Micron Technology, known to have internal reduction of the external supply voltage, showed a small degradation effect at early failures after stress at 10 V and 70 °C. Experiments were then started at the Micron Technology 16-Mbit product, which has no internal reduction of the 3.3-V supply voltage. No degradation was detected for stresses up to 8 V at 70 °C although a higher internal voltage was reached as in the 5-V product. It would be interesting to continue the experiment on the 16-Mbit device to higher stress voltages and compare the results to conventional reliability data published by the manufacturer for this device. In a side effort, the question was investigated on the …